Embodiments of the present invention generally relate to methods and apparatus for semiconductor processing. Specific embodiments pertain to methods and apparatus to minimize or eliminate dangling silicon bonds during semiconductor processing.
It is well known that p-n type diodes are not feasible for solar cells due to the following factors: (1) the doping capability of amorphous Si:H (a-Si:H) is rather poor; (2) doping has a detrimental effect on a-Si:H layer quality because the dopants lead to the creation of many additional Si dangling bonds, which are the main recombination centers in this material; and (3) in a classical p-n type diode, carrier collection is obtained by minority carrier diffusion within p- and n-type layers.
For crystalline silicon (especially single crystal silicon), the diffusion lengths for dopants are longer than 200 μm, which ensures the superior collection efficiency at one end of the diodes. However, such a diffusion length (for minority carrier) is very small, less than 0.1 μm in most a-Si:H. To resolve this problem, p-i-n diodes are always used for a-Si:H, with each layer (p-, i- and n-region) being extremely thin. The total thickness of the three layers is usually about 0.2 μm-0.3 μm.
The similar situation is also true for micro-crystalline Si:H (μ-Si:H) as well. Due to the relaxation of the requirement of μ—Si:H (longer minority carrier diffusion length), the total thickness of the n-i-p structure of μ-Si:H could be around 1.5-3 μm, though the n-layer and p-layer are still extremely thin.
In either a-Si:H layers or μ-Si:H layers, there are quite a few silicon dangling bonds within the films, partially due to the low temperature process. These dangling bonds are the recombination centers for carrier. In order to reduce the amount of the dangling bonds, the common practice is to perform a forming gas anneal (e.g., with 5-10% H2 in N2 gas) at elevated temperature. However, it is known in semiconductor processing that the temperature has to be as high as 400° C. to make such a forming gas anneal effective (e.g., to reduce negative bias temperature instability and gate oxide integrity problems for devices). Normally, such an anneal is performed at the aluminum alloy formation step for the bond-pad.
In solar cell production, the thermal budget is quite limited due to many concerns. The commonly used plasma enhanced chemical vapor deposition (PECVD) temperature, for a-Si:H with p-i-n or μ-Si:H with n-i-p, is around 200° C. or below. Then, the highest temperature one can use for any process after the silicon deposition is less than 200° C. At this temperature, the forming gas anneal will not effectively passivate the silicon dangling bonds in PECVD formed films.
However, if in-situ low temperature (e.g., 200° C.) hydrogen plasma is applied, hydrogen ions could have high energy and large energy dispersion. These H+ ions could have major detrimental impacts on the transparent conductive oxide (TCO) film (e.g., indium oxide and tin oxide) which is deposited prior to the silicon film deposition.
Therefore, there is a need in the art for methods and apparatus to improve the low temperature passivation efficiency of semiconductors.